Profile

Dr. Joan Carletta

Dr. Joan Carletta

Title: Associate Professor
Department: Electrical and Computer Engineering
Office: ASEC 261
Phone: 330-972-5993
Fax: 330-972-6487
Email: carlett@uakron.edu

Biography

Degrees

Doctor of Philosophy in Computer Engineering, Case Western Reserve University, 1995.
Bachelor of Science in Electrical Engineering, State University of New York at Buffalo, 1998.

Teaching Experience

Associate Professor, Department of Electrical and Computer Engineering, The University of Akron, 2005 - present.
Assistant Professor, Department of Electrical and Computer Engineering, The University of Akron, 1999 - 2005.
Assistant Professor, Department of Computer Engineering and Science, Case Western Reserve University, 1995 - 1999.

Professional Societies

Association for Computing Machinery, 1998 to present.
Institute of Electrical and Electronics Engineers, 1995 to present.

Honors and Awards

Chosen for NASA/ASEE Summer Faculty Fellowship Program at NASA Glenn Research Center, 1998 and 1999.
Named a Glennan Fellow for outstanding new teachers/scholars (one of five CWRU faculty so named), 1998 - 1999.
Recipient of Best Paper Award, 1994 IEEE VLSI Test Symposium.

Professional Activities

Member, IEEE Women in Engineering committee, 2007.
Co-initiative Leader, IEEE Educational Activity Board Initiative: Increasing the Representation of Women in IEEE's Fields of Interest, 2007.
Technical review work for the following journals and conferences:
IEEE Transactions on Circuits and Systems -- II: Analog and Digital Signal Processing
IEEE Transactions on Computer-Aided Design of Integrated Circuits
IEEE Transactions on VLSI Systems
Measurement, Journal of the International Measurement Confederation IMEKO
Journal of Electronic Testing: Theory and Applications
IEE Proceedings - Circuits, Devices and Systems
IEEE International Test Conference
IEEE VLSI Test Symposium
IEEE/ACM Design Automation Conference
Session Chair, IEEE International Test Conference, 2000.

Research Accomplishments

Interests
Real-time computing for digital signal processing applications
VLSI and VLSI design automation
Field programmable gate arrays

Funded Research

With J. Zhe and J. Hu of the University of Akron, IDBR: Development of a Multiplexed Microfluidic Coulter Counting Instrument, National Science Foundation's Instrumentation Development for Biological Research Program, $583,106 over three years, September 2007 to August 2010.

With Masters student C. Bakula, Investigating Pulse-Shaping Filters for Lunar Surface Networks, Ohio Aerospace Institute's Program for Stipend-Supported Student Residencies at NASA Glenn Research Center for Studies in Lunar Exploration, $27,000, January 2007 to June 2007.

Analysis of Optimal Bit-Depth for Image and Signal Processing Implementation in Field Programmable Gate Arrays, University of Akron Research Foundation (for Lockheed Martin), $25,000, March 2004 to December 2004.

With A. Bell of the Virginia Polytechnic Institute and State University, ITR/Collaborative Research: FPGA Wavelet Image Compression Systems for Mobile Wireless Networks, National Science Foundation Information Technology Research Program, $300,000, September 2002 to August 2005.

With R. Veillette, ITR/AP: Reconfigurable Computing for Real-Time Control Systems, National Science Foundation Information Technology Research Program, $201,901, September 2001 to August 2003.

Real-Time Control of a Magnetic Bearing Using Field Programmable Gate Arrays, UA Faculty Research Grant, $3500, September 2000.

Real-Time Control of a Magnetic Bearing Using Field Programmable Gate Arrays, UA College of Engineering's Firestone Research Initiative, $5,000, September 2000.

An Experimental Evaluation of Methods for VLSI Partitioning, Computing Research Association: Computing Research Experience for Women, $6,500, 1998.

Publications

Recent Journal Publications

J. Zhe, A. Jagtiani, P. Dutta, J. Hu, and J. Carletta, A Micromachined High-Throughput Resistive Pulse Sensor for Bioparticle Detection and Counting, Journal on Micromechanics and Microengineering, vol. 17, no. 2, February 2007, pp. 304-313.
A.V. Jagtiani, J. Zhe, J. Hu, and J.E. Carletta, Detection and Counting of Micro-Scale Particles and Pollen Using a Multi-Aperture Coulter Counter, Measurement Science and Technology, vol. 17, no. 7, July 2006, pp. 1706-1714.
K.A. Kotteri, A.E. Bell, and J.E. Carletta, Multiplierless Filter Bank Design: Methods that Improve Both Hardware and Image Compression Performance, IEEE Transactions on Circuits and Systems for Video Technology, vol. 16, no. 6, June 2006, pp. 776-780.
Z. Fang, J.E. Carletta, and R. Veillette, A Methodology for FPGA-based Control Implementation, IEEE Transactions on Control Systems Technology, vol. 13, no. 6, November 2005, pp. 977-987.
K.A. Kotteri, S. Barua, A.E. Bell, and J.E. Carletta, A Comparison of Hardware Implementations of the Biorthogonal 9/7 DWT: Convolution vs. Lifting, IEEE Transactions on Circuits and Systems II, vol. 52, no. 5, May 2005, pp. 256-260.
S. Barua, J.E. Carletta, K. Kotteri, and A.E. Bell, An Efficient Architecture for Lifting-based Two-Dimensional Discrete Wavelet Transforms, Integration - the VLSI Journal, vol. 38, no. 3, January 2005, pp. 341-352.
K.A. Kotteri, A.E. Bell, and J.E. Carletta, Design of Multiplierless, High-Performance, Wavelet Filter Banks with Image Compression Applications, IEEE Transactions on Circuits and Systems I, vol. 51, no. 3, March 2004, pp. 483-494.
J. Carletta, G. Giakos, N. Patnekar, L. Fraiwan and F. Krach, Design of a Field Programmable Gate Array-based Platform for Real-Time De-noising of Optical Imaging Signals Using Wavelet Transforms, Measurement, vol. 36, no. 3-4, October-December 2004, pp. 289-296.
K.A. Kotteri, A.E. Bell, and J. Carletta, Quantized FIR Filter Design Using Compensating Zeros, IEEE Signal Processing Magazine, vol. 20, no. 6, November 2003, pp. 60-67.
M. Nourani, J.E. Carletta, and C.A. Papachristou, Integrated Test of Interacting Controllers and Datapaths, ACM Transactions on Design Automation of Electronic Systems, vol. 6, no. 3, July 2001, pp. 401-422.
J.E. Carletta and C.A. Papachristou, Behavioral Testability Insertion for Datapath / Controller Pairs, Journal of Electronic Testing: Theory and Applications, vol. 11, no. 1, August 1997, pp. 9-28.

Education

Ph.D. Computer Engineering, Case Western Reserve University, 1995; B.S. Electrical Engineering, State University of New York at Buffalo, 1988

Courses

  • Courses Taught at The University of Akron
    • 4400:693 VLSI Design and Development, Spring 2001.
    • 4450:693 FPGAs and Embedded Systems, Springs 2005 and 2006, Fall 2007.
    • 4450:480/693 High Performance Computing/Advanced Processor Design, Springs 2001 to 2004.
    • 4400:360 Physical Electronics, Falls 2000 and 2006.
    • 4450:370 VLSI Design, Springs 2000 to 2007.
    • 4450:470/570 VLSI Circuits and Systems, Falls 1999 to 2002, 2004 to 2007.
    • 4400:101 Tools for Electrical and Computer Engineering (lab section), Falls 2000 and 2006.
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  • Courses Taught at Other Universities
    • Logic Design of Digital Systems, junior-level undergraduate course, Fall 1995 and Fall 1996.
    • Research in VLSI Design Automation, graduate course, Springs 1996, 1997, and 1998.
    • Special Topics in Computer Science, senior-level undergraduate course, Fall 1998 and Spring 1999.
    • Logic Design and Computer Organization, junior-level undergraduate course, Fall 1998.
      •

    • Students

  • Yang Wang, M.S. in progress (co-advisor).

  • Wei (Vivian) Feng, M.S. in progress.

  • Xinggao Xia , M.S. in progress.

  • Xin (Cindy) Jiang, Ph.D. in progress.

  • Firas Hassan , Ph.D. in progress.

  • Casey Bakula, M.S. in progress.

  • Vamsi Annavajjula, 'A Failure Accommodating Battery Management System with Individual Cell Equalizers and State of Charge Observers,' Masters thesis, 2007, The University of Akron. Co-advised with Dr. T. Hartley.

  • Sami Khorbotly, Design and Implementation of Low Cost De-Noising Systems for Real-Time Control Applications, Ph.D. dissertation, 2007, The University of Akron.

  • Hima Bindu Damecharla, FPGA Implementation of a Parallel EBCOT Tier-1 Encoder that Preserves Encoding Efficiency, Masters thesis, 2006, The University of Akron.

  • Sankar Barua, A High-Performance Hardware Architecture for Lifting-based Discrete Wavelet Transforms for Image Compression Applications, Masters thesis, 2004, The University of Akron.

  • Zhengwei (Vicky) Fang, A Methodology for the Fixed-Point Implementation of Digital Infinite Impulse Response Filters on Field Programmable Gate Arrays, Ph.D. dissertation, 2004, The University of Akron.

  • Frederick W. Krach, Design and Implementation of FPGA-based Control Using Digital Redesign for a Magnetic Bearing Application, Masters thesis, 2003, The University of Akron.

  • Elie Yarack, Toward Both a Time and Solution Efficient Multi-Way Partitioning, Masters thesis, 1999, Case Western Reserve University.

  • Mark C. Brighton, Datapath Placement using Simulated Annealing for the Virtex Family of Field Programmable Gate Arrays, Masters project, 1999, Case Western Reserve University.

  • Marina Rabinovich, Netlist Clustering Enhancer Algorithm as It Relates to Improving VLSI Partitioning, Masters project, 1999, Case Western Reserve University.

  • Aaron Carkin, Simulating 3-Dimensional Environments Using Fisheye Video, Masters project, 1999, Case Western Reserve University.

  • Mark Kuemerle, Design and Intelligent Power Control of an Asynchronous Floating Point Unit, Masters project, 1997, Case Western Reserve University.